(1) Field of the Invention
This invention is concerned with a semiconductor device and a method of manufacturing it, and in particular relates to a semiconductor device and a method of manufacturing it wherein a diffusion regions at a surface of the semiconductor substrate and an electrode layer made of polycrystalline silicon are self-aligned. And this invention further, relates to the construction of a memory element and a method of manufacturing it. Such memory elements are utilized both in semiconductor memory devices and in CPUs etc. which incorporate a semiconductor memory. The invention relates in particular to the construction of a memory element for a read-only memory (ROM) and to a method of manufacturing it.
(2) Description of the Prior Art
Recent years have seen rapid progress in semiconductor technology. In the future, it will become necessary to work at even greater precision and to reduce the alignment tolerance between different layers, in order to increase the level of circuit integration. The preferred strategy for improving the alignment tolerance, i,e, reducing it, is self-alignment between the layers. In particular, self-alignment of contacts and/or direct contacts is important for increasing the level of circuit integration. However, the present situation is that there is no fully established technique for self-alignment of direct contacts between polycrystalline silicon and diffusion regions.
Semiconductor devices such as redundant n-channel MOSICs wherein the polycrystalline silicon has direct contact with the diffusion regions, have conventionally been manufactured by the method described below with reference to FIG. 1(a) to (e).
First of all, as shown in FIG. 1(a), a p type silicon substrate 1 is selectively oxidized to form a field oxide layer 2 and island-shaped oxide films, isolated by field oxide layer 2, are formed on the surface of substrate 1 by thermal oxidization. A first polycrystalline silicon layer is then formed over the entire surface. Next, this polycrystalline silicon layer is doped with an impurity such as phosphorus, then gate electrode 3 is formed by patterning the polycrystalline silicon layer. Gate oxide film 4 is then formed by selectively etching the oxide film, using this gate electrode 3 as a mask, n type diffusion regions 5.sub.1, 6.sub.1 are then formed by doping the surface of substrate 1 with an n type impurity such as phosphorus, using gate electrode 3 as a mask.
Next, as shown in FIG. 1(b), a CVD-SiO.sub.2 film 7 is deposited over the entire surface, and a resist pattern 8 is formed on this CVD-SiO.sub.2 film 7 by photolithography. After this, direct contact holes 9 are formed by selectively etching the CVD-SiO.sub.2 film 7, using the resist pattern 8 as a mask, as shown in FIG. 1(c).
Next, a second polycrystalline silicon later 10 is deposited over the whole surface. Phosphorus is then thermally diffused into this second polycrystalline silicon layer 10 under for example a POCl.sub.3 atmosphere, and passes through this polycrystalline silicon layer 10 to form highly doped n.sup.+ type diffusion regions 5.sub.2 and 6.sub.2 in n type diffusion regions 5.sub.1 and 6.sub.1 and situated at greater depth than said n type diffusion regions 5.sub.1 and 6.sub.1. In this way, drain region 11 consisting of n type diffusion region 5.sub.1 and n.sup.+ type diffusion region 5.sub.2 and source region 12 consisting of n type diffusion region 6.sub.1 and n.sup.+ type diffusion region 6.sub.2 are respectively formed, as shown in FIG. 1(d). The MOSIC is then completed by patterning second polycrystalline silicon layer 10 to form electrode layer 13 connected through direct contact holes 9 to drain region 11 and source region 12 respectively, as shown in FIG. 1(e).
However, since direct contact holes 9 are formed using resist pattern 8 (formed by photolithography) as a mask, in the above-described method shown in manufacture of FIG. 1, a mask alignment tolerance has to be provided. Consequently, an alignment tolerance is needed between gate electrode 3 and field oxide layer 2. This presents an obstacle to increasing the level of circuit integration.
A method of manufacturing a semiconductor device has recently been announced in IEDM, whereby direct contact can be achieved in a self-aligned manner. This method will now be described with reference to FIG. 2 (a) to (e).
First of all, as shown in FIG. 2(a), a field oxide layer 22 is formed by selective oxidation of p type silicon substrate 21 and islands of oxide film isolated by field oxide layer 22 are formed on the surface of substrate 21 by thermal oxidation. A first polycrystalline silicon layer is then formed over the entire surface. After this, the polycrystalline silicon layer is doped with impurity such as phosphorus, then gate electrode is formed by patterning the polycrystalline silicon layer. Gate oxide film 24 is then formed by selective etching of the oxide film using gate electrode 23 as a mask. N type diffusion regions 25.sub.1 and 26.sub.1 are then formed by doping the surface of substrate 21 with an n type impurity, such as phosphorus, using gate electrode 23 as a mask.
Wet oxidation treatment is then performed. In this process, as shown in FIG. 2(b), the polycrystalline silicon is oxidized at a greater rate than the monocrystalline silicon, so a comparatively thick oxide film 27 is formed around the gate electrode 23 consisting of polycrystalline silicon and a comparatively thin oxide film 28 is formed on the exposed surface of monocrystalline silicon substrate 21. Resist pattern 29 is then formed by photolithography on field oxide layer 22.
Direct contact holes 30 are then formed by etching until thin oxide film 28 of the surface of substrate 21 is completely removed. As shown in FIG. 2(c), oxide film 27 remains around gate electrode 23.
Next, resist pattern 29 is removed, and second polycrystalline silicon layer 31 is deposited. Then phosphorus is thermally diffused through polycrystalline silicon layer 31 into second polycrystalline silicon layer 31 under for example a POC1.sub.3 atmosphere, so as to form highly doped n.sup.+ type diffusion regions 25.sub.2 and 26.sub.2 situated at greater depth than n type diffusion regions 25.sub.1 and 26.sub.1. In this way, as shown in FIG. 2(d), drain region 32 consisting of n type diffusion region 25.sub.1 and n.sup.+ type diffusion region 25.sub.2 and source region 33 consisting of n type diffusion region 26.sub.1 and n.sup.+ type diffusion region 26.sub.2 are respectively formed. As shown in FIG. 2(e), the MOSIC is then completed by patterning second polycrystalline silicon layer 31 to form electrode layer 34 connected through direct contact holes 30 to drain region 32 and source region 33, respectively.
With the method of manufacture described above and illustrated in FIG. 2, direct contact holes 30 can be formed in a self-aligned manner with respect to gate electrode 23 and field oxide layer 22. This makes it possible to produce MOSICs of a high degree of intergration. However, with such a method, the angle of gate electrode 23 after wet oxidation treatment is sharp, and the thickness of oxide film 27 around gate electrode 23 becomes very thin because of the etching, so there is a decrease in the breakdown voltage.
Furthermore, the normally used ROMs are also called "mask program ROMs" because the data is written into them in the wafer manufacturing process using a mask. There are three commonly used ways of writing the data into such a ROM. The first way is the contact method. The second is the so-called S (source) D (drain) G (gate) method, in which the data is written by the presence or absence of transistors. The third is a method in which the threshold voltage of the transistors is altered in accordance with the written data. A further distinction may be made based on the circuit configuration of the memory cell, between NOR type ROMs and NAND-NOR type ROMs. Yet a further distinction may be made based on the system in which the ROMs are used, between synchronous ROMs and asynchronous ROMs. NOR type ROMs are suited to high-speed operation and NAND-NOR type ROMs are used for slower speeds.
In the above classification of ROMs based on the circuit configuration of the memory cell, for NOR type ROMs (which are suited to high-speed operation), the contact arrangement is often adopted. This is because this arrangement is effective in meeting production requirements, because, in addition to ease of circuit design and reliablility of data writing, in such ROMs the step of data writing is in the latter half of the total sequence of steps.
FIG. 3 is a plan view of the pattern showing the configuration of the memory cell area of a conventional ROM utilized in this contact method. In the Figure, the region enclosed by a broken line is a single memory cell 301. A plurality of memory cells are arranged in the horizontal direction and in the vertical direction. A single memory cell 301 is constituted by a single MOS transistor. In more detail, memory cell 301 comprises: a drain diffusion region 302; a source diffusion region 303 common to the MOS transistors arranged in the horizontal direction in the drawing; word line 304 constituted by a polycrystalline silicon layer which constitutes the common gate electrode of the MOS transistors arranged in the horizontal direction; and data line 306 made of aluminum and selectively connected through contact hole 305 in accordance with the written date to the drains (diffusion region 302) of the MOS transistors arranged in the vertical direction in the drawing.
FIG. 4 is an equivalent circuit diagram of a ROM having as pattern as shown in FIG. 3. In as contact type ROM, as its name implies, data is written when contacts are formed in the wafer process, so the presence or absence of contact by virtue of contact hole 305 corresponds to data "1" or "0".
In the case of a ROM having a pattern as shown in FIG. 3, diffusion region 302, which constitutes the drain of the memory cell MOS transistor is connected to data line 306 through contact hole 305. Diffusion region 302 is made of silicon while data line 306 is made of a metal such as aluminum. Their work functions are therefore different. To make the contact resistance of materials of different work functions sufficiently small, contact hole 305 has to have a large area. The distance between the periphery of contact hole 305 and the periphery of diffusion region 302 also has to be sufficiently large to prevent short-circuiting with the substrate. Consequently the area occupied by diffusion regions 302 of the respective drains becomes large, so that the area of a single memory cell 301 becomes large. In the case of a ROM of large memory capacity, this results in a large chip area, increasing costs.
The present inventors have already invented the ROM whose pattern is shown in plan view in FIG. 5 and in cross-section in FIG. 6 with the object of eliminating the above-mentioned drawbacks possessed by the conventional ROM. This ROM is described in the specification of Japanese patent application No. Sho. 58-75026 and a resume of this description will now be given. In this ROM, n channel MOS transistors are used as the memory cells. In FIG. 5, the region enclosed by the broken line is a single memory cell 510. A plurality of memory cells are arranged in a matrix configuration in the horizontal and vertical directions. As in FIG. 3 described above, a single memory cell is constituted by a single MOS transistor. N.sup.+ type regions 512 constituting the drains of each memory cell 510 are provided in a p type silicon semiconductor substrate 511. N.sup.+ region 513 is provided extending in the horizontal direction in substrate 511 and constitutes a common source region of the plurality of memory cells arranged in the horizontal direction in the drawing. Word line 514, consisting of a first polycrystalline silicon layer and constituting the common gate electrode of the plurality of memory cells arranged in the horizontal direction is provided extending so as to cut across horizontally between n.sup.+ regions 512 and 513 in the plurality of memory cells arranged in the horizontal direction. The surface of n.sup.+ region 512 constituting the drain of each of the memory cells is connected with wiring layer 516 consisting of a second polycrystalline silicon layer, through contact holes 515 formed in each memory cell of two rows arranged in the horizontal direction. The end portion of this wiring layer 516 is arranged so as to extend as far as word line 514 constituting the common gate electrode. Data line 518 made of aluminum and selectively connected (through contact holes 517 provided in accordance with the written data) with n.sup.+ region 512 (constituting the drain) is provided in common for the plurality of memory cells arranged in the horizontal direction.
FIG. 6 is a cross-sectional view along the line X--X in FIG. 5 showing the construction of a single memory cell. Numeral 520 designates the field oxide film for element isolation. Numeral 521 designates the oxide film provided below word line 514, and 522 to 524 are respectively oxide films. Inversion prevention region 525 is provided on the surface of substrate 511 below field oxide film 520.
In a ROM constructed as above, instead of the data line 518 (made of aluminum) being directly connected to n.sup.+ region 512 (constituting the drain of the memory cell transistors), first of all, wiring layer 516 (made of polycrystalline silicon) is connected through contact hole 515 to part of the surface of n.sup.+ region 512, and then in turn this wiring layer 516 is itself connected to data line 518 (made of aluminum) through contact holes 517 that are selectively provided in accordance with the written data. Since both n.sup.+ type region 512 and wiring layer 516 are made of silicon, their work functions are equivalent. This makes it possible to make the contact resistance between the two sufficiently small even though the area of contact is restricted, and thereby enables the area of contact holes 515 on n.sup.+ type region 512 to be reduced. Also, when n.sup.+ type region 512 and wiring layer 516 are connected through contact holes 515, field oxide film 520 can have a self-aligned construction, so that contact holes 515 can maintain a suitable distance with respect to the word line 514 only. The area of n.sup.+ type region 512 itself can therefore be made sufficiently small. In terms of memory cell area this enables a reduction of 20 to 50% over that of the FIG. 3 construction described above.
On the other hand, when effecting a connection between data line 518 (made of aluminum) and wiring layer 516 (made of polycrystalline silicon), these two substances having different work functions, wiring layer 516 extends to above word line 514, and its planar distance is made sufficiently longer than n.sup.+ type region 512. The area of the contact holes 517, which constitute the region of connection between data line 518 and wiring layer 516, can therefore be made sufficiently great, irrespective of the size of the area of n.sup.+ type region 512. This enables high density of circuit integration to be achieved without adverse effects on the voltage and current characteristics of the transistors produced by the magnitude of the contact resistance (which is determined by the area of the contact hole).
Thus, with the ROM shown in FIG. 5, a considerable reduction in cell size can be attained compared with the ROM described above as shown in FIG. 3. However, even with such cells, when the dimensions are scaled down in order to increase memory capacity, as shown in FIG. 6, the margin A which is left in forming of the contact holes (buried contact holes) 515 to allow for possible mis-alignment and the distance B likewise including a margin for mis-alignment, in order to guarantee the requisite area of contact, occupy a large part of the cell. As there are limits to the degree to which it is possible to improve the accuracy of mask alignment, large increases in the density of circuit integration cannot be expected unless this problem is solved.